2016年12月22日星期四

HD LED Display Brought The Challenges to the LED Chip (Part 2)

Chip-side solution

1. Reduce the size of the chip size reduction

On the surface, is the problem of layout design, it seems that as long as the need to design a smaller map can be resolved. However, the chip size can continue indefinitely down? the answer is negative. There are several reasons to limit the extent of chip size reduction:

(1) packaging processing restrictions. During the packaging process, two factors limit the size of the chip. First, the nozzle limit. Solid crystal need to draw the chip, the chip must be greater than the short edge of the nozzle diameter. There are currently cost-effective nozzle diameter of 80um or so. Second, wire restrictions. First, the wire electrode that chip electrode must be large enough, otherwise the reliability of wire can not be guaranteed, the industry reported minimum electrode diameter 45um; followed by the distance between the electrodes must be large enough, otherwise the two must be mutual interference between the wire.

(2) chip processing restrictions. Chip processing, there are two restrictions. One is the layout layout limitations. In addition to the limitations of the package end, the size of the electrode, the electrode spacing is required, the electrode and the MESA distance, the width of the road, the boundaries of different layers have their limits, the current characteristics of the chip, SD process capability, lithography processing capacity Determines the scope of the specific restrictions. In general, the minimum distance from the P electrode to the edge of the chip is limited to 14 μm or more.


The second is the ability to crack processing constraints. SD scribing + mechanical lobe process has a limit, the chip size is too small may not be lobed. When the diameter of the wafer increases from 2 to 4 inches, or to 6 inches in the future, the difficulty of dicing the lobes increases, that is, the chip size can be processed increases. 4 inch chip, for example, if the chip length of less than 90μm short side, aspect ratio greater than 1.5: 1, the yield loss will increase significantly.

Based on the above reasons, I boldly predicted that the chip size reduced to 17mil2, the chip design and process capability close to the limit, the basic no longer reduce the space, unless the chip technology solutions have a big breakthrough.

2. Brightness boost

Brightness enhancement is the eternal theme of the chip side. Chip factory through the extension of the program to optimize the quantum effect, through the chip structure adjustment to enhance the external quantum effect.

However, on the one hand chip size will inevitably lead to reduce the size of the light-emitting area, chip brightness decreased. On the other hand, small pitch screen dot pitch narrow, single-chip brightness demand has declined. There is a complementary relationship between the two, but to leave the bottom line. At present, chip-side in order to reduce costs, mainly in the structure to do subtraction, which usually have to pay the cost of reducing brightness, so how trade-off is the industry to pay attention to.

3. Consistency at low current

The so-called small current, is relatively common indoor, outdoor chip trial current is. As shown in the following diagram, the chip I-V curve, the conventional indoor, outdoor chip work in the linear work area, the current is large. The small pitch LED chip needs to work near the zero point of the non-linear work area, the current is too small.

In the non-linear work area, LED chip by the semiconductor switching threshold, the difference between the chip is more obvious. It is easy to see that the discrepancy of the nonlinear workspace is much larger than that of the linear workspace, because of the analysis of the brightness and wavelength dispersion of the high-volume chips. This is the inherent challenge of the chip side.

The way to deal with this problem is to optimize the direction of the epitaxy to reduce the lower limit of the main linear work area; followed by the chip on the optical optimization, the different characteristics of the chip to distinguish.

4. Parasitic capacitance consistency

At present, there is no condition on the chip to directly measure the capacitance of the chip. Capacitance characteristics and the relationship between conventional measurement items is not clear, the industry has to be summed up. Chip-side optimization of the direction of the epitaxy on the one adjustment, one sub-file on the electrical refinement, but the cost is high, not recommended.

5. Reliability

Chip-side reliability can be described in the chip package and the parameters of the aging process. But overall, the reliability of the chip on the screen after the impact of factors, focusing on ESD and IR two.

ESD refers to antistatic ability. According to IC industry reports, more than 50% of the chip failure and ESD. To improve chip reliability, must enhance the ESD capability. However, in the same wafer, the same chip structure, the chip size will inevitably bring smaller ESD capacity weakened. This is directly related to the current density and chip capacitance characteristics and can not be resisted.

IR is the reverse leakage current, usually measured at a fixed reverse voltage reverse current value of the chip. IR reflects the number of defects within the chip. The larger the IR value, the more the chip is defective.

To enhance ESD performance and IR performance, must be epitaxial structure and chip structure to make more optimization. In the chip sub-file, through strict sub-file standard, you can effectively put the ESD performance and weak IR chip removed, thereby enhancing the chip on the screen after the reliability.

2016年12月15日星期四

HD LED Display Brought The Challenges to the LED Chip (Part 1)


LED display compared to other display technology, with self-luminous, excellent color reproduction, high refresh rate, power save, easy maintenance and other advantages. High brightness, large size can be achieved through the mosaic of these two characteristics, that is the LED display in the past two decades decisive factor in high-speed growth. In the field of large-screen outdoor display, no other technology can compete with the LED display technology so far.

But LED display also has its shortcomings in the past, such as lamp packaging between the large spacing, that make in lower resolution, not suitable for indoor and close viewing. In order to improve the resolution, it is necessary to reduce the distance between the lamp, but reduce the size of the lamp, although it improve the screen resolution, and the cost will rise rapidly

In recent years, with efforts of the chip manufacturing and packaging manufacturers, IC circuit manufacturers and screen manufacturers and others, single-package device cost is getting lower and lower, LED packaging devices smaller and smaller, smaller screen pixel spacing, Resolution is getting higher and higher, making small-pitch LED display in the indoor large-screen display of the advantages more and more obvious.

At present, the small pitch LED is mainly used in advertising media, sports venue, stage background, municipal engineering and other fields, and also in the transportation, broadcasting, military and other fields continue to open the new market. Expected to 2018, the market size were close to 10 billion. Can be predicted in the next few years, small pitch LED display will continue to expand market share, and squeeze the DLP rear projection market space. Everbright Securities Research Institute, according to forecasts, by 2020, small pitch LED display with DLP rear projection of the replacement rate will reach 70% to 80%.

The following we start from the product design, technology point of view to discuss the development of small pitch LED display on the blue and green LED chip demand, as well as chip-side may take the response program.

Small pitch LED display with the demand on LED chip

As the core of the LED display, LED chip played a crucial role in the small pitch display developing process. The current achievements and future development of small pitch LED display are depends on the tireless efforts of the chip side.

On the one hand, The pitch of indoor LED display from the early P4 gradually reduced to P1.5, P1.0, there is the developing of P0.8. Corresponding to the size of led lamp from 3535,2121 reduced to 1010, and some manufacturers to develop the size of 0808,0606, and even some manufacturers are developing size 0404.

As all we know, encapsulation lamp to reduce the size, will inevitably require the chip size reduction. At present, the common small pitch led display use the blue green chip surface area of about 30mil2, part of the chip factory has been in production 25mil2, or even 20mil2 chip.

On the other hand, the smaller the surface area of the chip, the lower brightness of the single chip, a series of problems affecting the display quality become prominent.

One of the difficulties of the small pixel pitch LED display is the “low brightness and low  gray, That is the gray level is not enough in the low brightness, in order to realize the low brightness and high gray, at present the package is used black bracket ,due to weak support to the chip reflective of black bracket, so requires the LED chip t have enough brightness.

The second is the display uniformity problem, compared with the common display, small pixel pitch will appear afterglow, first sweep of the dark, low bright red and low gray, uneven and other issues, At present, for the afterglow, the first scan of the dark and low gray and other issues, Package side and IC control side have made the effort. effective mitigation of these problems, the brightness of the low gray level of the problem is also through point by point correction technology to ease. However, as one of the root causes of the problem, the chip needs to pay more effort, specifically, the small current brightness and uniformity is better, the consistency of the parasitic capacitance is better.

The third is the problem of reliability, the current industry standard is LED dead lamp rate to allow the value of 1/10000, obviously not suitable for small pixel pitch LED display, because the pixel density is large of small pixel pitch display ,the viewing distance of near, If 10000pcs led lamp, there are 1 piece failure lamp, the effect is not acceptable. the failure lamp rate of the future needs to be controlled at 1/100000 or even a part of a million to meet the needs of long-term use.

In general, with the development of small pixel pitch LED, the demand for LED chip: size reduction, the relative brightness promotion, small current brightness uniformity, good parasitic capacitance consistency, high reliability.